It is known with respect to integrated circuits to realize certain functions with the aid of so-called switched capacitors (SCs), for example the function of an ohmic resistor. As is known, the impedance of a capacitor can be calculated from the reciprocal value of the product of frequency and capacitance. Accordingly, for simulating ohmic resistors, integrated capacitors are controlled via switches, so that a continuous reloading operation takes place at the capacitor. The frequency of the control signal is matched to the capacitance of the capacitor such that the desired impedance is obtained.
When ohmic resistors are simulated with the aid of switched capacitors, considerable chip area can be saved even in consideration of the elements required for the switching operation.
For switching the capacitor, an insulated gate field effect transistor (IGFET) is usually employed, and it is possible to make use of complementary transistors. Of course, endeavors will be made in most cases to render possible a high switching speed.
The consequence thereof in practical application is to keep the entire charge transfer as low as possible and to make the response speed to the pulse-shaped control signals as high as possible.
When for switching a transistor a standard field-effect transistor is used, for example, which is controlled with the pulse-shaped signal and which has is source drain path arranged between the signal input and a terminal or plate of the capacitor, parasitic effects play a role that is not negligible. This shall be elucidated in more detail hereinafter with reference to the accompanying FIGS. 1a and 1b and 2 of the specification.
FIG. 1a shows a typical low-pass filter having a series resistor R and a parallel capacitor C. Using switched capacitors, this circuit can be designed without the ohmic resistor R, as shown in FIG. 1b. Resistor R has been replaced by a capacitor and a switch disposed in parallel thereto, which can be shorted in an intermittent manner by a signal .phi..sub.1 and which has a further switch connected in series therewith that is periodically coupled to the downstream capacitor C' by a second, not overlapping signal .phi..sub.2.
FIG. 2 depicts a circuit arranged between an input terminal receiving a signal Vi and an output terminal delivering an output signal Vo. The upper plate of switched capacitor Cs is connected to the input via two transistor switches T1 and T2. The two transistor switches are each formed as IGFET and are fed at the gate thereof with signal .phi. and .phi., respectively. The source-drain path of T1 is arranged between the input and the upper plate of Cs, the same holding also for transistor switch T2, however, with a short-circuit connection being present here between source and drain.
FIG. 3 shows the equivalent circuit diagram of the arrangement depicted in FIG. 2. First, the transistor switch depicted to the left in FIG. 2 and FIG. 3 shall be explained. The equivalent circuit diagram contains ohmic resistor Rds.sub.off, which is the ohmic resistor in the channel between source and drain when the transistor is switched off.
Between the insulated gate and the source as well as between the insulated gate and drain, there is a (parasitic) capacitance Cgs.sub.T1 and Cgd.sub.T1, respectively.
FIG. 4 shows, in greatly exaggerated manner, the path of the rear edge of signal .phi. and the front edge of signal .phi., respectively. Within a period of time .DELTA.t, the voltage of .phi. decreases and the voltage of .phi. increases, respectively, by .DELTA.V.
Without transistor switch T2, the capacitance Cgd.sub.T1 thus acts on the capacitor Cs to be switched. Thus, solely by the parasitic capacitance of the transistor switch T1, a load having an influence on Cs and thus requiring consideration, results in accordance with the following equation: EQU .DELTA.Q=Cgs.multidot..DELTA.v (1)
In the usual design of field effect transistors in integrated circuits, it can be assumed here for reasons of simplification EQU Cgs=Cgd (2)
Consequently, this means that the parasitic capacitances of the insulated gate are of equal value with respect to source and with respect to drain.
The parasitic capacitance introduced by the transistor switch has to be taken into consideration in the design of the circuit and the operation thereof, since the value .DELTA.Q according to above equation (1) constitutes a charge amount that has to be transported in addition to the charge stored in capacitor Cs. An erroneous overall charge transfer leads to erroneous operation of the circuit in total.
The effects of the parasitic capacitance between the gate and the drain of T1 can be eliminated with the aid of the second transistor switch T2 in FIG. 2.
As shown in the equivalent circuit diagram in FIG. 3, second transistor switch T2 also has a series resistor and two parallel capacitors each set such that their capacitance is half of the parasitic capacitance between the insulated gate and the drain of T1, for example. As will still be explained hereinafter, the parasitic capacitance Cgd.sub.T1 is compensated by the two parasitic capacitances of transistor switch T2 when the parasitic capacitances thereof are each half as large as the one parasitic capacitance of T1. This is indicated in FIG. 3 on the right-hand side by the designations 1/2 (Cgd.sub.T2) and 1/2 (Cgs.sub.T2), respectively. On the condition that Cgd.sub.T2 =1/2 (Cgs.sub.T1), the desired value EQU .DELTA.Q=0
then is obtained as compensated charge .DELTA.Q from EQU .DELTA.Q=(2.multidot.Cgd.sub.T2 -Cgs.sub.T1).DELTA.v (3)
With the arrangement shown in FIG. 3, i.e., a switched capacitor C.sub.s, a transistor switch T1 arranged between one plate of the switched capacitor and the input, and a compensation component (compensation transistor) T2 connected in series therewith, an arrangement is created in which undesired parasitic effects of the transistor switch T1 can be compensated.
When the transistor switch T1 is formed on as little chip area as possible, the overall chip area of the transistor switches required for numerous switched capacitors can be minimized. The smallest dimensions for individual structures of the integrated transistor switch are predetermined by several effects, for example the specific manufacturing process for making the IC chip. When looking at the equivalent circuit diagram of FIG. 3, one can see that the transistor switch T1 itself can be realized with the smallest possible structures; for achieving the effect that the two parasitic capacitors of switch T2 in FIG. 3 have half the capacitance of one of the two parasitic capacitors of transistor switch T1 each, it is possible at the most to minimize the structures of component T2, but not those of transistor switch T1. The structures of transistor switch T1 in general have to be twice as large as those of component T2.
Thus, in designing the circuit it is necessary first to determine the structure for component T2, and on the basis of this the construction of T1 is determined, with the dimensions of the latter, in particular the channel length (cp. length 1 min in FIG. 5) between source and drain, being twice as large as in component T2.
These marginal conditions are not only undesirable for the reason that relatively much chip area is necessary for the switches of the switched capacitor. Since the conditions are such as elucidated by way of FIG. 3, the parasitic capacitances of transistor switch T1 in addition are relatively large, and the charge amount to be transferred is correspondingly large.